Some registers (RAMPX, RAMPY) may not be present on machines with less than 64 KiB of addressable memory.Ī typical ATmega memory map may look like:Įxtended I/O registers (memory-mapped I/O only) The special-purpose CPU registers, with the exception of PC, can be accessed as I/O registers. These are usually written as "0x00 (0x20)" through "0x3F (0x5F)", where the first item is the I/O address and the second, in parentheses, the data address. They have therefore two different addresses. The first 64 I/O registers are accessible through both the I/O and the data address space. The general purpose registers, the status register and some I/O registers are bit-addressable, with bit 0 being the least significant and bit 7 the most significant.The EEPROM is memory-mapped in some devices in others, it is not directly addressable and is instead accessed through address, data and control I/O registers.For the purpose of fetching constant data, program memory is addressed bytewise through the Z pointer register, prepended if necessary by RAMPZ.Program memory ( flash) has a separate address space, addressed as 16-bit words for the purpose of fetching instructions.The data address space maps the 32 general-purpose registers, all the I/O registers (including those also accessible through the I/O address space), and the RAM it can be addressed either directly or indirectly through the X, Y and Z pointer registers, prepended if necessary by RAMPX, RAMPY and RAMPZ respectively.I/O registers have a dedicated 6-bit address space, the lower half of which is bit-addressable some parts have I/O registers outside this address space, which are called "extended I/O" and are only accessible as memory-mapped I/O in the data address space.
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The general purpose registers are addressed by their numbers (0–31), although the full 5-bit number is not stored in instructions that can only operate on a subset of those registers.The following address spaces are available: Special bit load and bit store instructions use this bit. This is an internal carry from additions and is used to support BCD arithmetic. Unique to AVR, this is always N⊕V, and shows the true sign of a comparison. Set in case of two's complement overflow. Set to a copy of the most significant bit of an arithmetic result. Set to 1 when an arithmetic result is zero. The INC and DEC instructions do not modify the carry flag, so they may be used to loop over multi-byte arithmetic operations. RAMPX, RAMPY, RAMPZ, RAMPD and EIND: 8-bit segment registers that are prepended to 16-bit addresses in order to form 24-bit addresses only available in parts with large address spaces.In addition to these 32 general-purpose registers, the CPU has a few special-purpose registers: Some variants of the MUL operation are limited to eight registers, R16 through R23. Instructions which allow an immediate value are limited to registers R16–R31 (8-bit operations) or to register pairs R25:R24–R31:R30 (16-bit operations ADIW and SBIW). Y and Z also support a six-bit positive displacement. Postincrement and predecrement addressing modes are supported on all three. The last three register pairs are used as pointer registers for memory addressing. The lower-numbered register of the pair holds the least significant bits and must be even-numbered. All arithmetic and logic operations operate on those registers only load and store instructions access RAM.Ī limited number of instructions operate on 16-bit register pairs. There are 32 general-purpose 8-bit registers, R0–R31.
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